1. Field of the Invention
The present invention relates to a semiconductor memory, and more particularly to an improvement in soft error immunity.
2. Description of the Background Art
FIG. 16 is a circuit diagram showing a conventional semiconductor memory 1R. FIG. 16 illustrates a memory cell 10R and accompanying two (i.e., a pair of) bit lines BL1R, BL2R and a word line WLR. The memory cell 10R is a memory cell of a so-called single port SRAM (Static Random Access Memory).
As shown in FIG. 16, the memory cell 10R is formed by two driver transistors 11DNR, 12DNR, two load transistors 11LPR, 12LPR, and two access transistors 11ANR, 12ANR. Access transistors may be called transfer transistors or transfer gates. In the conventional semiconductor memory 1R, the driver transistors 11DNR, 12DNR and access transistors 11ANR, 12ANR are each composed of an N-type (N-channel type) MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), while the load transistors 11LPR, 12LPR are each composed of a P-type (P-channel type) MOSFET.
The driver transistor 11DNR and load transistor 11LPR are connected in series to form a CMOS type inverter 11R. Likewise, the driver transistor 12DNR and load transistor 12LPR are connected in series to form a CMOS type inverter 12R. The two inverters 11R and 12R are connected in parallel between a power supply potential VDD and a ground potential GND.
A connection point 11bR between the driver transistor 11DNR and load transistor 11LPR, i.e., an output terminal 11bR of the inverter 11R is connected to the bit line BL1R through the access transistor 11ANR. Further, the output terminal 11bR of the inverter 11R is connected to an input terminal 12aR of the inverter 12R, that is, connected in common to the gates of the two transistors 12DNR and 12LPR. Likewise, a connection point 12bR between the driver transistor 12DNR and load transistor 12LPR, i.e., an output terminal 12bR of the inverter 12R is connected to the bit line BL2R through the access transistor 12ANR. Further, the output terminal 12bR of the inverter 12R is connected to an input terminal 11aR of the inverter 11R, that is, connected in common to the gates of the two transistors 11DNR and 11LPR. The gates of the access transistors 11ANR and 12ANR are both connected to the word line WLR.
Since the output terminals 11bR and 12bR of the inverters 11R and 12R correspond to so-called storage nodes of the memory cell 10R, these storage nodes are designated by the same reference characters 11bR and 12bR as the output terminals 11bR and 12bR for convenience""s sake.
Next, a specific structure of the conventional semiconductor memory 1R will be described referring to layout views (plan views) shown in FIGS. 17 to 21. For ease of description, part of components of the conventional semiconductor memory 1R shown in FIG. 17 is extracted and shown in FIGS. 18 to 21. Further, for ease of description, first and second directions D1 and D2 are indicated as being parallel to a main surface 5SR of a semiconductor substrate 5R and perpendicular to each other.
As shown in FIGS. 17 to 21, three wells WP1R, WNR and WP2R are formed in the main surface 5SR of the semiconductor substrate 5R and are aligned in this order in the first direction D1.
As shown in FIG. 18, an N-type driver transistor 11DNR and an N-type access transistor 11ANR are formed in the well WP1R of P-type. P-type load transistors 11LPR, 12LPR are formed in the well WNR of N-type. Further, an N-type driver transistor 12DNR and an N-type access transistor 12ANR are formed in the well WP2R of P-type.
Specifically, N+-type impurity regions FN32R, FN10R and FN20R constituting source/drain regions of N-type MOSFETs are formed in the main surface 5SR in the P-well WP1R. The impurity regions FN32R and FN10R are aligned in the second direction D2 with a channel region of the driver transistor 11DNR interposed therebetween, and the impurity regions FN10R and FN20R are aligned in the second direction D2 with a channel region of the access transistor 11ANR interposed therebetween. Here, the two transistors 11DNR and 11ANR share the impurity region FN10R.
Likewise, N+-type impurity regions FN33R, FN11R and FN21R are formed in the main surface 5SR in the P-well WP2R. The impurity regions FN33R and FN11R are aligned in the second direction D2 with a channel region of the driver transistor 12DNR interposed therebetween, and the impurity regions FN11R and FN21R are aligned in the second direction D2 with a channel region of the access transistor 12ANR interposed therebetween. Here, the two transistors 12DNR and 12ANR share the impurity region FN11R.
On the other hand, P+-type impurity regions FP12R, FP10R, FP13R and FP11R constituting source/drain regions of P-type MOSFETs are formed in the main surface 5SR in the P-well WP2R. The impurity regions FP12R and FP10R are aligned in the second direction D2 with a channel region of the load transistor 11LPR interposed therebetween, and the impurity regions FP13R and FP11R are aligned in the second direction D2 with a channel region of the load transistor 12LPR interposed therebetween.
The channel regions of the transistors 11DNR, 11LPR and 12ANR are aligned in the first direction D1, and the channel regions of the transistors 12DNR, 12LPR and 11ANR are aligned in the first direction D1.
A gate interconnect line PL11R is provided to be opposite to the channel regions of the transistors 11DNR and 11LPR with a gate oxide film (not shown) interposed therebetween. Further, the gate interconnect line PL11R is in contact with the impurity region FP11R. Likewise, a gate interconnect line PL12R is provided to be opposite to the channel regions of the transistors 12DNR and 12LPR with a gate oxide film (not shown) interposed therebetween. Further, the gate interconnect line PL12R is in contact with the impurity region FP10R. Likewise, gate interconnect lines PL11AR and PL12AR are provided to be opposite to the channel regions of the access transistors 11ANR and 12ANR, respectively, with a gate oxide film (not shown) interposed therebetween. The gate interconnect lines PL11R, PL12R, PL11AR and PL12AR are made of, e.g., low resistance polysilicon.
An interlayer insulation film (not shown) is provided to cover the impurity region FN32R and the like and the gate interconnect lines PL11R, PL12R, PL11AR and PL12AR. Contact holes CR reaching the impurity regions FN32R, FN10R, FN20R, FN33R, FN11R, FN21R, FP12R and FP13R, respectively, are formed in the interlayer insulation film. Further, a contact hole (also referred to as shared contact hole) SCR, to the inside of which the gate interconnect line PL11R and impurity region FP11R are both exposed, and a shared contact hole SCR, to the inside of which the gate interconnect line PL12R and impurity region FP10R are both exposed, are formed in the interlayer insulation film. Moreover, contact holes (also referred to as gate contact holes) GCR reaching the gate interconnect lines PL11AR and PL12AR, respectively, are further formed in the interlayer insulation film.
Next, as will be appreciated from FIGS. 18 and 19, first layer interconnect lines 1WR, 1GR, 1DR, 1B1R, 1B2R, 1L1R and 1L2R made of, e.g., aluminum are provided on the interlayer insulation film.
The two interconnect lines 1WR are in contact with the gate interconnect lines PL11AR and PL12AR, respectively, through the gate contact holes GCR, while the two interconnect lines 1GR are in contact with the impurity regions FN32R and FN33R, respectively, through the contact holes CR. Further, the two interconnect lines 1DR are in contact with the impurity regions FP12R and FP13R, respectively, through the contact holes CR. Furthermore, the interconnect lines 1B1R and 1B2R are in contact with the impurity regions FN20R and FN21R, respectively, through the contact holes CR.
The interconnect line 1L1R is in contact with the impurity regions FN10R, FP10R and the gate interconnect line PL12R through the contact hole CR and shared contact hole SCR. Likewise, the interconnect line 1L2R is in contact with the impurity regions FN11R, FP11R and the gate interconnect line PL11R through the contact hole CR and shared contact hole SCR.
An interlayer insulation film (not shown) is provided to cover these interconnect lines 1WR, 1GR, 1DR, 1B1R, 1B2R, 1L1R and 1L2R. The interlayer insulation film is provided with via holes 1TR, which are provided on the interconnect lines 1WR, 1GR, 1DR, 1B1R and 1B2R.
Next, as will be appreciated from FIGS. 19 and 20, second layer interconnect lines 2WR, 2GR, 2DR, 2B1R and 2B2R made of, e.g., aluminum are provided on the interlayer insulation film (not shown) covering the first layer interconnect lines 1WR, 1GR, 1DR, 1B1R, 1B2R, 1L1R and 1L2R. The interconnect lines 2WR, 2GR, 2B1R and 2B2R are in contact with the interconnect lines 1WR, 1GR, 1DR, 1B1R and 1B2R, respectively, through the via holes 1TR, while the interconnect line 2DR is in contact with the two interconnect lines 1DR through the via holes 1TR.
An interlayer insulation film (not shown) is provided to cover these interconnect lines 2WR, 2GR, 2DR, 2B1R and 2B2R. The interlayer insulation film is provided with via holes 2TR, which are provided on the two interconnect lines 2WR, respectively.
Further, as will be appreciated from FIGS. 20 and 21, a third layer interconnect line 3WR made of, e.g., aluminum is provided on the interlayer insulation film (not shown) covering the second layer interconnect lines 2WR, 2GR, 2DR, 2B1R and 2B2R. The interconnect line 3WR is in contact with the two interconnect lines 2WR through the via holes 2TR.
The interconnect lines 2B1R and 2B2R correspond to the bit lines BL1R and BL2R, respectively, and the interconnect line 3WR corresponds to the word line WLR. The interconnect lines 2GR are connected to the ground potential GND, and the interconnect line 2DR is connected to the power supply potential VDD.
In the conventional semiconductor memory 1R having the above-described structure, the storage node 11bR is formed to include the impurity regions FN10R and FP10R, and the storage node 12bR is formed to include the impurity regions FN11R and FP11R. Thus, soft errors occur when xcex1-rays or neutrons are made incident to these impurity regions FN10R, FP10R, FN11R and FP11R. Particularly, the N+-type impurity region FN10R which belongs to the driver transistor 11DNR and access transistor 11ANR formed in the same well WP1R and the N+-type impurity region FN11R which belongs to the driver transistor 12DNR and access transistor 12ANR formed in the same well WP2R are greatly responsible for the occurrence of soft errors. Since the soft error immunity of the conventional semiconductor memory 1R is determined only by the capacity of the storage nodes 11bR and 12bR, a decrease in the capacity of the storage nodes 11bR and 12bR with miniaturization causes deterioration in the soft error immunity.
An object of the present invention is to provide a semiconductor memory with improved soft error immunity as compared to the conventional semiconductor memory 1R.
According to the present invention, a semiconductor memory includes a semiconductor substrate and a memory cell formed in the semiconductor substrate. The memory cell includes first and second inverters and first and second access transistors. The first inverter has a first input terminal and a first output terminal. The first inverter further has at least one MISFET of a first conductivity type as a first driver transistor. The at least one MISFET has a main terminal connected to the first output terminal. The second inverter has a second input terminal connected to the first output terminal and a second output terminal connected to the first input terminal. The second inverter further has at least one MISFET of the first conductivity type as a second driver transistor. The at least one MISFET has a main terminal connected to the second output terminal. The first access transistor is formed by a MISFET of the first conductivity type having a main terminal connected to the first output terminal. The second access transistor is formed by a MISFET of the first conductivity type having a main terminal connected to the second output terminal. The semiconductor substrate includes first to third wells of a second conductivity type opposite to the first conductivity type. The first to third wells are not in contact with one another. The first and second access transistors are both formed in the first well. The first driver transistor is formed in the second well. The second driver transistor is formed in the third well.
Since the first and second access transistors are both formed in the first well, impurity regions constituting the main terminals of the first and second access transistors are both formed in the first well. Thus, the effect of common mode noise can improve the soft error immunity. Further, the impurity regions of the first and second access transistors are formed in the first well, while those of the first and second driver transistors are formed in the second and third wells, respectively, that are not in contact with the first well. Thus, the soft error immunity can be improved as compared to the structure in which access transistors and driver transistors are formed in the same well.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.